VERILOG HDL

What is verilog HDL?

A hardware description language is a computer language that is used to describe hardware. There are two HDLs are widely used are verilog HDL and VHDL (Very H igh Speed Integrated Circuit Hardware Description Language). Schematic design entry can be replaced by writing HDL code that CAD tools understand. CAD tools can verify the HDL codes, and create the circuits automatically from HDL codes.

Why use verilog?  

• Verilog is more popular in industry than VHDL 
• They offer similar features

History of Verilog..  

• In 1980s, originally developed by Gateway Design Automation. 
• In 1990, was put in public domain.  
• In 1995, adopted as an IEEE standard 1364-1995  
• In 2001, an enhanced version, Verilog 2001

Functions of Verilog HDL..  

• Design entry (using schematics or HDL) 
• Simulation and verification of the design  
• Synthesis

Verilog can be used to design complex digital circuits  

• Complex circuits can be divided into simpler and synthesizable circuit blocks.
• There are hundreds of Verilog syntaxes that can be used and they will be introduced in several stages through this course when the language elements are relevant to the design topics. 
  
• For complete Verilog syntaxes, refer to reference books.

PROJECT TITLE

To develop flexible traffic light using verilog HDL to describe the hardware implementation. Usually,during congested traffic hours, a police traffic will take over the traffic light and standing at the middle of the road junction to control the traffic flow. Flexible mode will take over the normal mode function of traffic light to control the traffic. This project will be implemented using verilog HDL. Then it will be programmed into Altera DE2 board for proof the concept.

SCHEDULE FYP1

• Registration for final year project (FYP) in FYP website

• Attend final year project (FYP) briefing at UNIKL British-Malaysian Institute (BMI) on Thursday at 2.30pm.

• Get information for new procedure about final year project (FYP) namely update profile in http://fyp.bmi.unikl.edu.my and create blog as a progress report for every week.

• All the final year project (FYP) student need to choose supervisor to guide them for making the task for project proposal.

• So, I already choose Sir Suhaimi Bahisham bin Jusoh@Yusoff as my supervisor to assist me doing my task very well. I have to select the project title for FYP and my project title is Development of Flexible Traffic Light Using Verilog HDL.

• Research about project " Development of Flexible Traffic Light Using Verilog HDL 

• Meet supervisor to discuss about my project before submit the proposal.

• Submit draft of final year project (FYP) proposal to the supervisor (Sir Suhaimi Bahisham).